A 15-bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (vol 40, pg 1047, 2005)

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Liu, HC	en_US
dc.contributor.author	Lee, ZM	en_US
dc.contributor.author	Wu, JT	en_US
dc.date.accessioned	2014-12-08T15:18:11Z	-
dc.date.available	2014-12-08T15:18:11Z	-
dc.date.issued	2005-11-01	en_US
dc.identifier.issn	0018-9200	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/JSSC.2005.859253	en_US
dc.identifier.uri	http://hdl.handle.net/11536/13141	-
dc.language.iso	en_US	en_US
dc.title	A 15-bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (vol 40, pg 1047, 2005)	en_US
dc.type	Correction	en_US
dc.identifier.doi	10.1109/JSSC.2005.859253	en_US
dc.identifier.journal	IEEE JOURNAL OF SOLID-STATE CIRCUITS	en_US
dc.citation.volume	40	en_US
dc.citation.issue	11	en_US
dc.citation.spage	2339	en_US
dc.citation.epage	2339	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000232947000025	-
dc.citation.woscount	0	-
顯示於類別：	期刊論文

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