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dc.contributor.authorHuang, HWen_US
dc.contributor.authorWang, CYen_US
dc.contributor.authorJou, JYen_US
dc.date.accessioned2014-12-08T15:18:21Z-
dc.date.available2014-12-08T15:18:21Z-
dc.date.issued2005-10-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2005.852032en_US
dc.identifier.urihttp://hdl.handle.net/11536/13244-
dc.description.abstractIn this paper, a novel strategy for designing the heterogeneous tree multiplexer is proposed. The authors build the multiplexer delay model by curve fitting and then formulate the heterogeneous tree multiplexer design problem as a special type of optimization problem called mixed-integer nonlinear programming (MINLP). A new design parameter, the switch size in each stage, is introduced to improve the speed of the heterogeneous tree multiplexer. The proposed strategy can determine the multiplexer architecture and the switch size in each stage simultaneously. Three optimization methods are provided to synthesize the heterogeneous tree multiplexer according to the design specifications.en_US
dc.language.isoen_USen_US
dc.subjectcapacitanceen_US
dc.subjectmodelingen_US
dc.subjectoptimizationen_US
dc.subjectsimulationen_US
dc.subjecttransistor sizingen_US
dc.titleAn efficient heterogeneous tree multiplexer synthesis techniqueen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2005.852032en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume24en_US
dc.citation.issue10en_US
dc.citation.spage1622en_US
dc.citation.epage1629en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000232235600011-
dc.citation.woscount2-
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