標題: Optimal Floating Gate Potential for Extending Data Retention of Post-Baking Method in Sub-20 nm Triple Level per Cell NAND Flash Memory
作者: Hsu, Yu-Cheng
Lin, Wei
Chang, Chun-Yen
電機學院
電子工程學系及電子研究所
College of Electrical and Computer Engineering
Department of Electronics Engineering and Institute of Electronics
關鍵字: NAND Flash Memory;Program/Erase (PE) Cycling;Post-Baking Method
公開日期: Jul-2016
摘要: A post-baking method with an optimized data pattern is developed to eliminate the program/erase (PE) cycle-induced damage of sub-20 nm NAND Flash memory and to improve its reliability. The electric field of the tunneling oxide (E-ox)-dependent oxide recovery is discussed in detail. The experimental results reveal that additional traps in the tunneling oxide are induced by the E-ox during the baking process via an electron-phonon interaction and the effectiveness of oxide recovery is reduced by the generation of these additional traps. Hence, the additional traps degrade the read margin and retention ability. Therefore, an optimized data pattern is produced to minimize E-ox and reduce the number of additional traps formed during the post-baking process. When the optimized data pattern is utilized in post-baking, the endurance of the sub-20 nm three-level-per-cell (TLC) NAND Flash memory is quadruple improved under one year retention condition.
URI: http://dx.doi.org/10.1166/jnn.2016.11588
http://hdl.handle.net/11536/132927
ISSN: 1533-4880
DOI: 10.1166/jnn.2016.11588
期刊: JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY
Volume: 16
Issue: 7
起始頁: 7295
結束頁: 7300
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