Superior Data Retention for Sub-20 nm Triple Level Per Cell NAND Flash Memory by Using a Novel Data Programming Method

Abstract

This work presents a novel data programming method for sub-20 nm triple level per cell (TLC) NAND Flash memory. The proposed method improves data retention ability and reduces the data failure rate of Embedded Multi Media Card (eMMC) during the high temperature reflow of surface mount technology (SMT). More than owing to the high temperature stress, the failure is closely related to the data pattern of the adjacent cell array. The proposed data programming method generates an optimized dummy data pattern based on the data of the last data word line (WL) and, then, programs the optimized dummy data pattern to the word line next to the data edge one to suppress the abrupt electrical potential energy drops caused by the erase data. The graded electrical potential energy can thus reduce the electric field and electron tunneling probability. Furthermore, the row bit error rate (RBER) with the high temperature stress of the last data word line can be reduced 85% by using the novel data programming method. This work also attempts to identify the root cause of the temperature and adjacent data pattern dependent retention by measuring and performing statistical analysis of a sub-20 nm TLC NAND Flash memory chip. 3D numerical simulation with comprehensive quantum tunneling models is also conducted to facilitate the theoretical analysis. Statistical and numerical analysis results indicate that a severe threshold voltage (Vth) shift of the memory cell occurs when the adjacent floating gate (FG) has both high and low Vth states. Above results demonstrate the feasibility of the proposed data programming method in generating the optimized dummy data pattern.