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dc.contributor.authorHuang, CCen_US
dc.contributor.authorWu, JTen_US
dc.date.accessioned2014-12-08T15:18:29Z-
dc.date.available2014-12-08T15:18:29Z-
dc.date.issued2005-09-01en_US
dc.identifier.issn1057-7122en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2005.852198en_US
dc.identifier.urihttp://hdl.handle.net/11536/13299-
dc.description.abstractThis paper presents a background calibration technique for trimming the input-referred offsets of the comparators in a flash analog-to-digital converter (ADC) without interrupting the ADC's normal operation. For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. Binary feedback is then used to digitally adjust the comparator's offset so that the offset is minimized. All calibration procedures are performed in the digital domain. The calibration performance is characterized by the converging speed of the feedback loop and the offset fluctuation due to the disturbance of the ADC's input. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of the ADC's input, the BCC's offset quantized step size, and the threshold of an internal bilateral peak detector. The offset fluctuation of a BCC can be drastically reduced by employing a windowing mechanism. The use of windowed BCCs in a flash ADC can introduce nonmonotonic-threshold (NMT) effects which include an increase in calibration settling time and an increase in sigma(V-OS). The use of uncorrelated random chopping for neighboring BCCs can ensure the validity of offset detection and mitigate the NMT effects.en_US
dc.language.isoen_USen_US
dc.subjectcomparatoren_US
dc.subjectflash analog-to-digital converter (ADC)en_US
dc.subjectoffset calibrationen_US
dc.titleA background comparator calibration technique for flash analog-to-digital convertersen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2005.852198en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume52en_US
dc.citation.issue9en_US
dc.citation.spage1732en_US
dc.citation.epage1740en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000232084300003-
dc.citation.woscount25-
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