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dc.contributor.authorHsieh, Dong-Ruen_US
dc.contributor.authorKuo, Po-Yien_US
dc.contributor.authorLin, Jer-Yien_US
dc.contributor.authorChen, Yi-Hsuanen_US
dc.contributor.authorChang, Tien-Shunen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2017-04-21T06:56:35Z-
dc.date.available2017-04-21T06:56:35Z-
dc.date.issued2017-02en_US
dc.identifier.issn0268-1242en_US
dc.identifier.urihttp://dx.doi.org/10.1088/1361-6641/32/2/025004en_US
dc.identifier.urihttp://hdl.handle.net/11536/133192-
dc.description.abstractIn this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.) similar to 110mV/dec., an extremely small drain induced barrier lowing (DIBL) similar to 12.2mVV(-1), and a high on/off ratio similar to 10(7) (V-D = 1V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.en_US
dc.language.isoen_USen_US
dc.subjectsidewall damascened techniqueen_US
dc.subjecttri-gateen_US
dc.subjectthin-film transistoren_US
dc.subjectstrain proximity free techniqueen_US
dc.subjectstress memorization techniqueen_US
dc.subjectrapid thermal annealingen_US
dc.subjectthree dimensional integrated circuitsen_US
dc.titleHigh-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization techniqueen_US
dc.identifier.doi10.1088/1361-6641/32/2/025004en_US
dc.identifier.journalSEMICONDUCTOR SCIENCE AND TECHNOLOGYen_US
dc.citation.volume32en_US
dc.citation.issue2en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Photonicsen_US
dc.identifier.wosnumberWOS:000393773600004en_US
Appears in Collections:Articles