標題: Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
作者: Huang, Chien-Chih
Wey, Chin-Long
Chen, Jwu-E
Luo, Pei-Wen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Design;Performance;Theory;Analog-to-digital converter (ADC);successive-approximation-register (SAR) ADC;unit capacitor;common-centroid;routing-aware placement;spatial correlation
公開日期: Nov-2015
摘要: The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratiomismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.
URI: http://dx.doi.org/10.1145/2770872
http://hdl.handle.net/11536/133373
ISSN: 1084-4309
DOI: 10.1145/2770872
期刊: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
Volume: 21
Issue: 1
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