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dc.contributor.authorLiu, Ren-Shuoen_US
dc.contributor.authorChuang, Meng-Yenen_US
dc.contributor.authorYang, Chia-Linen_US
dc.contributor.authorLi, Cheng-Hsuanen_US
dc.contributor.authorHo, Kin-Chuen_US
dc.contributor.authorLi, Hsiang-Pangen_US
dc.date.accessioned2017-04-21T06:56:47Z-
dc.date.available2017-04-21T06:56:47Z-
dc.date.issued2016-04en_US
dc.identifier.issn0018-9340en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TC.2014.2345387en_US
dc.identifier.urihttp://hdl.handle.net/11536/133451-
dc.description.abstractNAND flash-based solid-state drives (SSDs), which can serve as the caches of hard disk drives, have gained popularity in large-scale, high-performance storage. A type of advanced error correction code for SSDs, low-density parity-check (LDPC), is required to mitigate a considerable number of errors in the raw data of NAND flash. However, LDPC imposes read performance overhead due to the complex decoding procedure of LDPC. In this paper, we propose an error-correcting cache (EC-Cache) that exploits "error locality", a characteristic of NAND flash memory, to improve the read performance of SSDs. We use the term "error locality" to refer to the property that the majority of errors in reads to the same flash page appear at the same positions until the page is erased. By caching detected errors, we can correct a significant portion of errors in the requested flash page prior to the LDPC decoding process. This design significantly reduces LDPC decoding overhead because the latency of LDPC is correlated with the number of errors in the input data. We conduct experiments, including flash characterization, LDPC simulation, and SSD simulation, to evaluate EC-Cache. The experimental results demonstrate that EC-Cache can improve the read performance of LDPC-based SSDs by up to 2:6 x.en_US
dc.language.isoen_USen_US
dc.subjectNAND flash memoryen_US
dc.subjectsolid-state drive (SSD)en_US
dc.subjectlow-density parity-check (LDPC)en_US
dc.subjectbit error and cacheen_US
dc.titleImproving Read Performance of NAND Flash SSDs by Exploiting Error Localityen_US
dc.identifier.doi10.1109/TC.2014.2345387en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTERSen_US
dc.citation.volume65en_US
dc.citation.issue4en_US
dc.citation.spage1090en_US
dc.citation.epage1102en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000372752600008en_US
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