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dc.contributor.authorWang, Po-Haoen_US
dc.contributor.authorTsai, Shang-Jenen_US
dc.contributor.authorTanjung, Rizalen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorWang, Jinn-Shyanen_US
dc.contributor.authorChen, Tien-Fuen_US
dc.date.accessioned2017-04-21T06:56:22Z-
dc.date.available2017-04-21T06:56:22Z-
dc.date.issued2016-06en_US
dc.identifier.issn0167-9260en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.vlsi.2016.01.001en_US
dc.identifier.urihttp://hdl.handle.net/11536/133617-
dc.description.abstractVoltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration. (C) 2016 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectCache memoryen_US
dc.subjectLow voltageen_US
dc.subjectTiming discrepancyen_US
dc.subjectTiming-failure toleranceen_US
dc.titleCross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processorsen_US
dc.identifier.doi10.1016/j.vlsi.2016.01.001en_US
dc.identifier.journalINTEGRATION-THE VLSI JOURNALen_US
dc.citation.volume54en_US
dc.citation.spage24en_US
dc.citation.epage36en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000374362900003en_US
Appears in Collections:Articles