完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHuang, Wen-Hsienen_US
dc.contributor.authorShieh, Jia-Minen_US
dc.contributor.authorShen, Chang-Hongen_US
dc.contributor.authorHuang, Tzu-Enen_US
dc.contributor.authorWang, Hsing-Hsiangen_US
dc.contributor.authorYang, Chih-Chaoen_US
dc.contributor.authorHsieh, Tung-Yingen_US
dc.contributor.authorHsieh, Jin-Longen_US
dc.contributor.authorYeh, Wen-Kuanen_US
dc.date.accessioned2017-04-21T06:56:33Z-
dc.date.available2017-04-21T06:56:33Z-
dc.date.issued2016-06-13en_US
dc.identifier.issn0003-6951en_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.4954175en_US
dc.identifier.urihttp://hdl.handle.net/11536/133933-
dc.description.abstractA doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 x 10(18) cm(-3) and high crystallinity (Raman FWHM similar to 4.54 cm(-1)). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an I-on/I-off ratio over 10(5) and drain-induced barrier lowering of 168mV/ V. Moreover, the fast programming speed of 100 mu s-1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics. Published by AIP Publishing.en_US
dc.language.isoen_USen_US
dc.titleJunction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processesen_US
dc.identifier.doi10.1063/1.4954175en_US
dc.identifier.journalAPPLIED PHYSICS LETTERSen_US
dc.citation.volume108en_US
dc.citation.issue24en_US
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Photonicsen_US
dc.identifier.wosnumberWOS:000379037200062en_US
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