完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hou, Fu-Ju | en_US |
dc.contributor.author | Sung, Po-Jung | en_US |
dc.contributor.author | Hsueh, Fu-Kuo | en_US |
dc.contributor.author | Wu, Chien-Ting | en_US |
dc.contributor.author | Lee, Yao-Jen | en_US |
dc.contributor.author | Li, Yiming | en_US |
dc.contributor.author | Samukawa, Seiji | en_US |
dc.contributor.author | Hou, Tuo-Hung | en_US |
dc.date.accessioned | 2017-04-21T06:55:16Z | - |
dc.date.available | 2017-04-21T06:55:16Z | - |
dc.date.issued | 2016-10 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2016.2597317 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134196 | - |
dc.description.abstract | A feasible pathway to scale germanium (Ge) FETs in future technology nodes has been proposed using the tunable diamond-shaped Ge nanowire (NW). The Ge NW was obtained through a simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The different etching selectivity of surface orientations for Cl-2 and HBr was employed for the three-step isotropic/anisotropic/isotropic dry etching. The ratio of Cl-2 and HBr, mask width, and Ge recess depth were crucial for forming the nearly defect-free suspended Ge channel through effective removal of dislocations near the Si/Ge interface. This technique could also be applied for forming diamond-shaped Si NWs. The suspended diamond-shaped NW gate-all-around NWFETs feature excellent electrostatics, the favorable {111} surfaces along the < 110 > direction with high carrier mobility, and the nearly defect-free Ge channel. The pFET with a high I-ON/I-OFF ratio of 6 x 10(7) and promising nFET performance have been demonstrated successfully. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | {111} | en_US |
dc.subject | gate-all-around (GAA) | en_US |
dc.subject | germanium (Ge) | en_US |
dc.subject | isotropic/anisotropic etching | en_US |
dc.subject | nanowire (NW) | en_US |
dc.title | Suspended Diamond-Shaped Nanowire With Four {111} Facets for High-Performance Ge Gate-All-Around FETs | en_US |
dc.identifier.doi | 10.1109/TED.2016.2597317 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 63 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 3837 | en_US |
dc.citation.epage | 3843 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000384575700003 | en_US |
顯示於類別: | 期刊論文 |