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dc.contributor.authorHou, Fu-Juen_US
dc.contributor.authorSung, Po-Jungen_US
dc.contributor.authorHsueh, Fu-Kuoen_US
dc.contributor.authorWu, Chien-Tingen_US
dc.contributor.authorLee, Yao-Jenen_US
dc.contributor.authorLi, Yimingen_US
dc.contributor.authorSamukawa, Seijien_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.date.accessioned2017-04-21T06:55:16Z-
dc.date.available2017-04-21T06:55:16Z-
dc.date.issued2016-10en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2016.2597317en_US
dc.identifier.urihttp://hdl.handle.net/11536/134196-
dc.description.abstractA feasible pathway to scale germanium (Ge) FETs in future technology nodes has been proposed using the tunable diamond-shaped Ge nanowire (NW). The Ge NW was obtained through a simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The different etching selectivity of surface orientations for Cl-2 and HBr was employed for the three-step isotropic/anisotropic/isotropic dry etching. The ratio of Cl-2 and HBr, mask width, and Ge recess depth were crucial for forming the nearly defect-free suspended Ge channel through effective removal of dislocations near the Si/Ge interface. This technique could also be applied for forming diamond-shaped Si NWs. The suspended diamond-shaped NW gate-all-around NWFETs feature excellent electrostatics, the favorable {111} surfaces along the < 110 > direction with high carrier mobility, and the nearly defect-free Ge channel. The pFET with a high I-ON/I-OFF ratio of 6 x 10(7) and promising nFET performance have been demonstrated successfully.en_US
dc.language.isoen_USen_US
dc.subject{111}en_US
dc.subjectgate-all-around (GAA)en_US
dc.subjectgermanium (Ge)en_US
dc.subjectisotropic/anisotropic etchingen_US
dc.subjectnanowire (NW)en_US
dc.titleSuspended Diamond-Shaped Nanowire With Four {111} Facets for High-Performance Ge Gate-All-Around FETsen_US
dc.identifier.doi10.1109/TED.2016.2597317en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume63en_US
dc.citation.issue10en_US
dc.citation.spage3837en_US
dc.citation.epage3843en_US
dc.contributor.department電機學院zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000384575700003en_US
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