標題: Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO(2) high-k gate stacks
作者: Wu, WH
Chen, MC
Tsui, BY
How, YT
Yao, LG
Jin, Y
Tao, HJ
Chen, SC
Liang, MS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Aug-2005
摘要: This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO(2) high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO(2) high-k gate stacks.
URI: http://dx.doi.org/10.1143/JJAP.44.5977
http://hdl.handle.net/11536/13421
ISSN: 0021-4922
DOI: 10.1143/JJAP.44.5977
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS
Volume: 44
Issue: 8
起始頁: 5977
結束頁: 5981
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