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dc.contributor.authorLi, Kai-Shinen_US
dc.contributor.authorWu, Bo-Weien_US
dc.contributor.authorLi, Lain-Jongen_US
dc.contributor.authorLi, Ming-Yangen_US
dc.contributor.authorCheng, Chia-Chin Kevinen_US
dc.contributor.authorHsu, Cho-Lunen_US
dc.contributor.authorLin, Chang-Hsienen_US
dc.contributor.authorChen, Yi-Juen_US
dc.contributor.authorChen, Chun-Chien_US
dc.contributor.authorWu, Chien-Tingen_US
dc.contributor.authorChen, Min-Chengen_US
dc.contributor.authorShieh, Jia-Minen_US
dc.contributor.authorYeh, Wen-Kuanen_US
dc.contributor.authorChueh, Yu-Lunen_US
dc.contributor.authorYang, Fu-Liangen_US
dc.contributor.authorHu, Chenmingen_US
dc.date.accessioned2017-04-21T06:50:15Z-
dc.date.available2017-04-21T06:50:15Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-5090-0638-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/134338-
dc.description.abstractA U-shape MOS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MOS2 deposition, thin MOS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.en_US
dc.language.isoen_USen_US
dc.titleMOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 Availabilityen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGYen_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000390702200019en_US
dc.citation.woscount0en_US
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