完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chiu, Yi-Wei | en_US |
dc.contributor.author | Hu, Yu-Hao | en_US |
dc.contributor.author | Zhao, Jun-Kai | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.date.accessioned | 2017-04-21T06:50:06Z | - |
dc.date.available | 2017-04-21T06:50:06Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-4799-5341-7 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134365 | - |
dc.description.abstract | We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (V-MIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read V-MIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve V-MIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read V-MIN by 9% to 21% at low supply voltages. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A Subthreshold SRAM with Embedded Data-Aware Write-Assist and Adaptive Data-Aware Keeper | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.citation.spage | 1014 | en_US |
dc.citation.epage | 1017 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000390094701037 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |