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dc.contributor.authorHuang, Tzu-Chien_US
dc.contributor.authorHuang, Hong-Yien_US
dc.contributor.authorLiu, Jen-Chiehen_US
dc.contributor.authorCheng, Kuo-Hsingen_US
dc.contributor.authorLuo, Ching-Hsingen_US
dc.date.accessioned2017-04-21T06:50:02Z-
dc.date.available2017-04-21T06:50:02Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4244-9474-3en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/134394-
dc.description.abstractA fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390x390 um(2). The power consumption is 5.4 mW at 416 MHz.en_US
dc.language.isoen_USen_US
dc.titleAll Digital Phase-Locked Loop Using Active Inductor Oscillator and Novel Locking Algorithmen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage486en_US
dc.citation.epage489en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000297265300118en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper