標題: High Performance Silicon N-channel Gate-All-Around Junctionless Field Effect Transistors by Strain Technology
作者: Sung, P. -J.
Cho, T. -C.
Chen, P. -C.
Hou, F. -J.
Lai, C. -H
Lee, Y. -J.
Li, Y.
Samukawa, S.
Chao, T. -S.
Wu, W. -F.
Yeh, W. -K.
電子物理學系
電機工程學系
Department of Electrophysics
Department of Electrical and Computer Engineering
公開日期: 2016
摘要: In this paper, strain effects on silicon n-channel gate-allaround (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (I-on/I-off > 10(9)) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.
URI: http://hdl.handle.net/11536/134637
ISBN: 978-1-5090-1493-4
期刊: 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO)
起始頁: 174
結束頁: 175
Appears in Collections:Conferences Paper