1. You are Here：

Full metadata record
DC FieldValueLanguage
dc.contributor.authorSung, P. -J.en_US
dc.contributor.authorCho, T. -C.en_US
dc.contributor.authorChen, P. -C.en_US
dc.contributor.authorHou, F. -J.en_US
dc.contributor.authorLai, C. -Hen_US
dc.contributor.authorLee, Y. -J.en_US
dc.contributor.authorLi, Y.en_US
dc.contributor.authorSamukawa, S.en_US
dc.contributor.authorChao, T. -S.en_US
dc.contributor.authorWu, W. -F.en_US
dc.contributor.authorYeh, W. -K.en_US
dc.date.accessioned2017-04-21T06:48:50Z-
dc.date.available2017-04-21T06:48:50Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-5090-1493-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/134637-
dc.description.abstractIn this paper, strain effects on silicon n-channel gate-allaround (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (I-on/I-off > 10(9)) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.en_US
dc.language.isoen_USen_US
dc.titleHigh Performance Silicon N-channel Gate-All-Around Junctionless Field Effect Transistors by Strain Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO)en_US
dc.citation.spage174en_US
dc.citation.epage175en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000391840000050en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper


Related Contents
Loading...