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dc.contributor.authorChang, MFen_US
dc.contributor.authorWen, KAen_US
dc.date.accessioned2014-12-08T15:18:43Z-
dc.date.available2014-12-08T15:18:43Z-
dc.date.issued2005-08-01en_US
dc.identifier.issn0922-5773en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s11265-005-6252-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/13463-
dc.description.abstractWhen subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 mu m CMOS process are studied.en_US
dc.language.isoen_USen_US
dc.subjectROMen_US
dc.subjectSRAMen_US
dc.subjectsubstrate noiseen_US
dc.subjectsupply noiseen_US
dc.titlePower and substrate noise tolerance of configurable embedded memories in SoCen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s11265-005-6252-4en_US
dc.identifier.journalJOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGYen_US
dc.citation.volume41en_US
dc.citation.issue1en_US
dc.citation.spage81en_US
dc.citation.epage91en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000229936200007-
dc.citation.woscount2-
Appears in Collections:Articles


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