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dc.contributor.authorLuo, Guang-Lien_US
dc.contributor.authorKo, Chih-Hsinen_US
dc.contributor.authorWann, Clement H.en_US
dc.contributor.authorChung, Cheng-Tingen_US
dc.contributor.authorHan, Zong-Youen_US
dc.contributor.authorCheng, Chao-Chingen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.contributor.authorLin, Hau-Yuen_US
dc.contributor.authorChien, Chao-Hsinen_US
dc.date.accessioned2019-04-03T06:47:55Z-
dc.date.available2019-04-03T06:47:55Z-
dc.date.issued2012-01-01en_US
dc.identifier.issn1875-3892en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.phpro.2012.03.057en_US
dc.identifier.urihttp://hdl.handle.net/11536/134760-
dc.description.abstractThe selective growth of germanium into nanoscale trenches on silicon substrates was investigated. These nanoscale trenches-the smallest size of which was 50 nm-were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. It was found that the formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. It was considered that for the Ge grown in nanoscale Si areas (e. g., several tens of nanometers), the TDs were readily removed during cyclic thermal annealing, predominantly because their gliding distance to the SiO2 sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density. (C) 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of Garry Leeen_US
dc.language.isoen_USen_US
dc.subjectgermaniumen_US
dc.subjectdislocationsen_US
dc.subjectnano trechesen_US
dc.subjectepitaxyen_US
dc.titleNearly Dislocation-free Ge/Si Heterostructures by Using Nanoscale Epitaxial Growth Methoden_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1016/j.phpro.2012.03.057en_US
dc.identifier.journalINTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS SCIENCEen_US
dc.citation.volume25en_US
dc.citation.spage105en_US
dc.citation.epage109en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000305960300017en_US
dc.citation.woscount1en_US
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