標題: Simulation of Grain-Boundary Induced V-th Variability in Stackable NAND Flash Using a Voronoi Approach
作者: Yang, Ching-Wei
Chao, Shao-Heng
Su, Pin
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Grain boundary;polycrystalline silicon;stackable NAND flash;BE-SONOS;variability;Voronoi
公開日期: 2012
摘要: In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices.
URI: http://hdl.handle.net/11536/134764
ISBN: 978-1-4673-2848-7
期刊: 2012 12th Annual Non-Volatile Memory Technology Symposium
起始頁: 12
結束頁: 15
Appears in Collections:Conferences Paper