Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tsai, Hung-Yuan | en_US |
dc.contributor.author | Yang, Chi-Heng | en_US |
dc.contributor.author | Chang, Hsie-Chia | en_US |
dc.date.accessioned | 2017-04-21T06:48:17Z | - |
dc.date.available | 2017-04-21T06:48:17Z | - |
dc.date.issued | 2012 | en_US |
dc.identifier.isbn | 978-1-4673-2771-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134766 | - |
dc.description.abstract | This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384;124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An Efficient BCH Decoder with 124-bit Correctability for Multi-Channel SSD Applications | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2012 IEEE Asian Solid State Circuits Conference (A-SSCC) | en_US |
dc.citation.spage | 61 | en_US |
dc.citation.epage | 64 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000392841900016 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |