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dc.contributor.authorTsai, Hung-Yuanen_US
dc.contributor.authorYang, Chi-Hengen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2017-04-21T06:48:17Z-
dc.date.available2017-04-21T06:48:17Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-2771-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/134766-
dc.description.abstractThis paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384;124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency.en_US
dc.language.isoen_USen_US
dc.titleAn Efficient BCH Decoder with 124-bit Correctability for Multi-Channel SSD Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE Asian Solid State Circuits Conference (A-SSCC)en_US
dc.citation.spage61en_US
dc.citation.epage64en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000392841900016en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper