標題: A 5Gb/s Pulse Signaling Interface for Low Power On-Chip Data Communication
作者: Lin, Hung-Wen
Ho, Ying-Chieh
Fa, YingLin
Su, ChauChin
交大名義發表
National Chiao Tung University
公開日期: 2010
摘要: This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission gates to design inductive-peaking and non-clock hysteresis amplifiers. In 0.13um CMOS process, the proposed I/O occupies a total area of 0.07mm(2). At a bit rate of 5Gbps, the accumulated peak-to-peak jitter of overall I/O system and a 5mm of channel length is 76ps. And it consumes 8mW of power under 1.2V supply voltage or with a power efficiency of 0.32pJ/bit/mm.
URI: http://hdl.handle.net/11536/134853
ISBN: 978-1-4244-5309-2
ISSN: 0271-4302
期刊: 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
起始頁: 201
結束頁: 204
Appears in Collections:Conferences Paper