完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tang, Wei | en_US |
dc.contributor.author | Feng, Jianhua | en_US |
dc.contributor.author | Lee, Chunglen | en_US |
dc.date.accessioned | 2017-04-21T06:49:56Z | - |
dc.date.available | 2017-04-21T06:49:56Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-3868-6 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/ASICON.2009.5351194 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134922 | - |
dc.description.abstract | This paper presents a new on-chip jitter measurement circuit based on a dual vernier oscillator (VO) structure. The new structure measures the jitter with a low resolution VO first and then with a high resolution VO, thus greatly expanding the measurement range of the jitter and reducing the test time. The oscillators are implemented with differential digital controlled delay elements, whose oscillation periods can be precisely controlled The circuit has been implemented and verified with the SMIC 0.18 mu m technology and has been shown to have the ability of measuring jitters in the pico-second range. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | timing jitter | en_US |
dc.subject | on-chip | en_US |
dc.subject | vernier oscillator | en_US |
dc.subject | jitter measurement | en_US |
dc.title | A Jitter Measurement Circuit Based On Dual Resolution Vernier Oscillator | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.doi | 10.1109/ASICON.2009.5351194 | en_US |
dc.identifier.journal | 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | en_US |
dc.citation.spage | 1213 | en_US |
dc.citation.epage | + | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000275924100303 | en_US |
dc.citation.woscount | 1 | en_US |
顯示於類別: | 會議論文 |