完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Torres, Francisco | en_US |
dc.contributor.author | Srivastava, Rohit | en_US |
dc.contributor.author | Ruiz, Javier | en_US |
dc.contributor.author | Wen, H. -P. | en_US |
dc.contributor.author | Bose, Mrinal | en_US |
dc.contributor.author | Bhadra, Jayanta | en_US |
dc.date.accessioned | 2017-04-21T06:49:33Z | - |
dc.date.available | 2017-04-21T06:49:33Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-4868-5 | en_US |
dc.identifier.issn | 1089-3539 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134995 | - |
dc.description.abstract | Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture (TM) Technology-based SoC demonstrate about a 100x speedup on the emulator vis-a-vis the simulator. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Portable simulation/emulation stimulus on an industrial-strength SoC | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ITC: 2009 INTERNATIONAL TEST CONFERENCE | en_US |
dc.citation.spage | 623 | en_US |
dc.citation.epage | 623 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000279591000096 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |