標題: | Reliability Study of MANOS with and without a SiO2 Buffer Layer and BE-MANOS Charge-Trapping NAND Flash Devices |
作者: | Liao, Chien-Wei Lai, Sheng-Chih Lue, Hang-Ting Yang, Ming-Jui Shen, Chin-Yen Lue, Yi-Hsien Huang, Yu-Fong Hsieh, Jung-Yu Wang, Szu-Yu Luo, Guang-Li Chien, Chao-Hsin Hsieh, Kuang-Yeu Liu, Rich Lu, Chih-Yuan 電機學院 College of Electrical and Computer Engineering |
公開日期: | 2009 |
摘要: | The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E<10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS. |
URI: | http://hdl.handle.net/11536/135009 |
ISBN: | 978-1-4244-2784-0 |
期刊: | PROCEEDINGS OF TECHNICAL PROGRAM: 2009 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS |
起始頁: | 152 |
結束頁: | + |
顯示於類別: | 會議論文 |