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dc.contributor.authorTsai, Tzu-, Ien_US
dc.contributor.authorLee, Yao-Jenen_US
dc.contributor.authorChen, King-Shengen_US
dc.contributor.authorWang, Jeffen_US
dc.contributor.authorWan, Chia-Chenen_US
dc.contributor.authorHsueh, Fu-Kuoen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2017-04-21T06:49:10Z-
dc.date.available2017-04-21T06:49:10Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1891-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/135142-
dc.language.isoen_USen_US
dc.titleImpacts of a buffer layer and hi-wafers on the performance of strained-channel NMOSFETs with SiN capping layeren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2en_US
dc.citation.spage329en_US
dc.citation.epage+en_US
dc.contributor.department物理研究所zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentInstitute of Physicsen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000255857100169en_US
dc.citation.woscount0en_US
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