Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Mao, A. Y. | en_US |
dc.contributor.author | Lin, W. M. | en_US |
dc.contributor.author | Yang, Cw. | en_US |
dc.contributor.author | Hsieh, Y. S. | en_US |
dc.contributor.author | Cheng, L. W. | en_US |
dc.contributor.author | Lee, G. D. | en_US |
dc.contributor.author | Tsai, C. T. | en_US |
dc.contributor.author | Chung, S. S. | en_US |
dc.contributor.author | Ma, G. H. | en_US |
dc.date.accessioned | 2017-04-21T06:49:08Z | - |
dc.date.available | 2017-04-21T06:49:08Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-0584-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135147 | - |
dc.description.abstract | Reliability of ALD (Atomic Layer Deposition) HfSiON high K gate stacks is greatly enhanced with a property engineered IL (Interfacial Layer) between the gate dielectrics and the Si substrate. We report that the HfSiON, while deposited on an optimized plasma-based IL containing [N], exhibits strong resistance to the bombardment from heavy pocket implant species, achieving significantly reduced leakage and excellent reliability characteristics, compared to the HfSiON without an optimized IL and to the silicon oxynitride control wafers. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Reliability of ALD Hf-based high K gate stacks with optimized interfacial layer and pocket implant engineering | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | en_US |
dc.citation.spage | 50 | en_US |
dc.citation.epage | + | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000247059300023 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |