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dc.contributor.authorMao, A. Y.en_US
dc.contributor.authorLin, W. M.en_US
dc.contributor.authorYang, Cw.en_US
dc.contributor.authorHsieh, Y. S.en_US
dc.contributor.authorCheng, L. W.en_US
dc.contributor.authorLee, G. D.en_US
dc.contributor.authorTsai, C. T.en_US
dc.contributor.authorChung, S. S.en_US
dc.contributor.authorMa, G. H.en_US
dc.date.accessioned2017-04-21T06:49:08Z-
dc.date.available2017-04-21T06:49:08Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0584-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/135147-
dc.description.abstractReliability of ALD (Atomic Layer Deposition) HfSiON high K gate stacks is greatly enhanced with a property engineered IL (Interfacial Layer) between the gate dielectrics and the Si substrate. We report that the HfSiON, while deposited on an optimized plasma-based IL containing [N], exhibits strong resistance to the bombardment from heavy pocket implant species, achieving significantly reduced leakage and excellent reliability characteristics, compared to the HfSiON without an optimized IL and to the silicon oxynitride control wafers.en_US
dc.language.isoen_USen_US
dc.titleReliability of ALD Hf-based high K gate stacks with optimized interfacial layer and pocket implant engineeringen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage50en_US
dc.citation.epage+en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000247059300023en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper