Improvement on CDM ESD Robustness of High-Voltage Tolerant nLDMOS SCR Devices by Using Differential Doped Gate

Abstract

Early failure has been observed during CDM ESD stress on high-voltage tolerant nLDMOS-SCR devices in a standard low-voltage CMOS technology due to the gate oxide (GOX) degradation. In this work, we propose a special p+/n+ differential doped gate which boosts the CDM ESD failure current level with a factor of 3 to 9.