Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Pei-Yu | en_US |
dc.contributor.author | Tsui, Bing-Yue | en_US |
dc.date.accessioned | 2017-04-21T06:50:15Z | - |
dc.date.available | 2017-04-21T06:50:15Z | - |
dc.date.issued | 2014 | en_US |
dc.identifier.isbn | 978-1-4799-5677-7 | en_US |
dc.identifier.issn | 2161-4636 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135338 | - |
dc.description.abstract | 3D NAND Flash is the most promising memory architecture which can increase capacity continuously without aggressive scaling-down. The performance variability of the memory cell induced by the grain boundaries (GBs) of the poly-Si channel is a major concern. In this work, a full 3D simulation is performed to study the threshold voltage variability. The impact of the 3D structure geometry on the variation induced by the GB traps is discussed. In addition, a discrete-trap approach is also proposed to reflect the true behavior of the GB traps. A smaller variation in the discrete-trap approach is observed due to the local trap effect. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Simulation of Grain-Boundary Traps Effect for 3D Vertical Gate NAND Flash Memory Cell : From Structure Geometry to Trap Description | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000393376800083 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |