標題: | Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process |
作者: | Yeh, Chih-Ting Ker, Ming-Dou 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Electrostatic discharge (ESD);gate leakage;power-rail ESD clamp circuit;silicon-controlled rectifier (SCR) |
公開日期: | 2013 |
摘要: | A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45 mu m can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25 degrees C under the normal circuit operating condition with 1V bias. |
URI: | http://hdl.handle.net/11536/135409 |
ISBN: | 978-1-4799-0113-5 978-1-4799-0112-8 |
ISSN: | 1541-7026 |
期刊: | 2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) |
顯示於類別: | 會議論文 |