標題: Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM
作者: Shen, Chang-Hong
Shieh, Jia-Min
Wu, Tsung-Ta
Huang, Wen-Hsien
Yang, Chih-Chao
Wan, Chih-Jen
Lin, Chein-Din
Wang, Hsing-Hsiang
Chen, Bo-Yuan
Huang, Guo-Wei
Lien, Yu-Chung
Wong, Simon
Wang, Chieh
Lai, Yin-Chieh
Chen, Chien-Fu
Chang, Meng-Fan
Hu, Chenming
Yang, Fu-Liang
光電工程學系
Department of Photonics
公開日期: 2013
摘要: For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.
URI: http://hdl.handle.net/11536/135418
ISBN: 978-1-4799-2306-9
期刊: 2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Appears in Collections:Conferences Paper