完整後設資料紀錄
DC 欄位語言
dc.contributor.authorPan, Tung-Mingen_US
dc.contributor.authorYen, Li-Chenen_US
dc.contributor.authorChiang, Chien-Hungen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2017-04-21T06:48:35Z-
dc.date.available2017-04-21T06:48:35Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-60768-141-0en_US
dc.identifier.issn1938-5862en_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.3375608en_US
dc.identifier.urihttp://hdl.handle.net/11536/135564-
dc.description.abstractThe structure and electrical properties of a high-k Yb2TiO5 gate dielectric deposited on Si(100) substrates through reactive cosputtering were investigated. X-ray diffraction, X-ray photoelectron spectroscopy and atomic force microscopy were used to study the morphological and chemical features of these films as functions of the growth conditions. The Yb2TiO5 dielectrics annealed at 800 degrees C exhibited a thinner capacitance equivalent thickness, a lower gate leakage current, a smaller density of interface state, and a relatively lower hysteresis voltage compared to those at other annealing temperatures. These results are attributed to the formation of a rather well-crystallized Yb2TiO5 structure and composition.en_US
dc.language.isoen_USen_US
dc.titleInfluence of Postdeposition Annealing on Physical and Electrical Properties of High-k Yb2TiO5 Gate Dielectricsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1149/1.3375608en_US
dc.identifier.journalADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENTen_US
dc.citation.volume28en_US
dc.citation.issue1en_US
dc.citation.spage247en_US
dc.citation.epage252en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000313489900026en_US
dc.citation.woscount0en_US
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