完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Chia-Yi | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.date.accessioned | 2017-04-21T06:48:38Z | - |
dc.date.available | 2017-04-21T06:48:38Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-6455-5 | en_US |
dc.identifier.issn | 1948-3287 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135594 | - |
dc.description.abstract | This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many long scan chain switching activities. Based on two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. The proposed scheme skips many unnecessary don\'t care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed scheme illustrate the significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC\'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead and very few extra pins, and the power reduction is over 97%. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Scan chain | en_US |
dc.subject | Test-cost | en_US |
dc.subject | low power | en_US |
dc.title | A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010) | en_US |
dc.citation.spage | 237 | en_US |
dc.citation.epage | 243 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000393299700037 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |