標題: Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction
作者: Ying, Jen-Cheng
Tseng, Wang-Dauh
Tsai, Wen-Jiin
資訊工程學系
Department of Computer Science
關鍵字: capture power;low power testing;power consumption;scan-based testing;scan chain
公開日期: 1-七月-2019
摘要: High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a capture power minimization method to disable those scan chains, needless for the target fault detection, during the capture cycle for multi-scan testing. This method combines the scan chain clustering algorithm with the scan chain disabling technique to disable partial scan chains during the capture cycles while keeping the fault coverage unchanged. This method does not induce the capture violation problem nor does it increase the routing overhead. Experimental results for the large ISCAS'89 benchmark circuits show that this method can reduce the capture power by 43.97% averagely.
URI: http://dx.doi.org/10.6688/JISE.201907_35(4).0008
http://hdl.handle.net/11536/152607
ISSN: 1016-2364
DOI: 10.6688/JISE.201907_35(4).0008
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 35
Issue: 4
起始頁: 839
結束頁: 849
顯示於類別:期刊論文