A fast two-stage sample-and-hold amplifier for pipelined ADC application

doi:10.1109/DELTA.2008.58

標題:	A fast two-stage sample-and-hold amplifier for pipelined ADC application
作者:	Ruan, Jian Lee, Chung Len 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	sample-and-hold amplifier;two-stage structure;pipelined ADC;bootstrapped switch;bottom-plate sampling
公開日期:	2008
摘要:	This paper presents a differential input, two-stage structure sample-hold-amplifier (SHA) for which each stage can be designed and adjusted separately to have a large input dynamic range and fast operation speed. The clock feed through and charge injection is eliminated. The implemented SHA with a 0.18um 1.8V process shows that it can sample a 2.5 MHz signal at 40 MHz with a 63d8 SFDR and a -62 dB THD which is able to realize an ADC of 10 bit resolution.
URI:	http://dx.doi.org/10.1109/DELTA.2008.58 http://hdl.handle.net/11536/135645
ISBN:	978-0-7695-3110-6
DOI:	10.1109/DELTA.2008.58
期刊:	DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS
起始頁:	99
結束頁:	+
顯示於類別：	會議論文