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dc.contributor.authorChang, Jasper C. C.en_US
dc.contributor.authorHuang, Ryan H. -M.en_US
dc.contributor.authorLin, Louis Y. -Z.en_US
dc.contributor.authorWen, Charles H. -P.en_US
dc.date.accessioned2017-04-21T06:49:13Z-
dc.date.available2017-04-21T06:49:13Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4503-3520-1en_US
dc.identifier.issn0738-100Xen_US
dc.identifier.urihttp://dx.doi.org/10.1145/2744769.2744914en_US
dc.identifier.urihttp://hdl.handle.net/11536/135696-
dc.description.abstractTiming analysis becomes profound for modern VLSI designs. Functional timing analysis (FTA) has emerged to eliminate false paths and provide better timing closure than traditional static timing analysis (STA). However, signal transitions effect, such as multiple input switching (MIS), which changes the pin-to-pin delay of a gate as well as the overall circuit delay, has not yet been considered in FTA. Therefore, a Transition-Aware FTA (TA-FTA) engine using a novel four-valued encoding for calculating true delay under the signal-transition effect is developed in this work. However, timing analysis becomes sophisticated once the signal-transition effect is concerned. Therefore, two techniques, cone separation and filtering (CSF) and quadratic dynamic search (QDS), are also proposed to speed up TA-FTA by more than two orders in time. Experimental results shows that after considering the MIS effect, in the benchmark circuits, the delay reported by our TA-FTA increases by 23% on average and by 38% for the worst case.en_US
dc.language.isoen_USen_US
dc.subjectFTAen_US
dc.titleTA-FTA: Transition-Aware Functional Timing Analysis with A Four-Valued Encodingen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/2744769.2744914en_US
dc.identifier.journal2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000370268400167en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper