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dc.contributor.authorWu, Tse-Chingen_US
dc.contributor.authorChen, Chien-Juen_US
dc.contributor.authorChen, Yin-Nienen_US
dc.contributor.authorHu, Vita Pi-Hoen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2017-04-21T06:50:10Z-
dc.date.available2017-04-21T06:50:10Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-9094-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/135744-
dc.description.abstractIn this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage (CMOS)-M-2 latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (< 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.en_US
dc.language.isoen_USen_US
dc.subjectVerilog-A modelen_US
dc.subjecthybrid circuiten_US
dc.subjecttunneling FETen_US
dc.subjectFinFETen_US
dc.subjectlatchen_US
dc.subjectwork function variationen_US
dc.subjectfin line-edge roughnessen_US
dc.titleEvaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC)en_US
dc.citation.spage339en_US
dc.citation.epage344en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000380400500064en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper