完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yi, S. H. | en_US |
dc.contributor.author | Chin, Albert | en_US |
dc.date.accessioned | 2017-04-21T06:49:30Z | - |
dc.date.available | 2017-04-21T06:49:30Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4799-8364-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135768 | - |
dc.description.abstract | Power consumption is the crucial challenge for electronics. To lower the DC leakage power (P-DC), we applied the high-kappa gate dielectric to CMOS from the physics of Q equivalent to CV. More than 2 orders of magnitude lower P-DC is obtained at small 0.5 similar to 0.9 nm equivalent-oxide-thickness (EOT). The high-kappa dielectric also increases the charge controllability of flash memory and decrease the V-T disturbance by nearly cells, which improves cell density and cost. The AC power (P-AC) can be lowered by using high-mobility Ge CMOS at a lower V-D and 3D IC with a small capacitance, from basic physics of P-AC equivalent to CV(D)(2)f/2. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | ultra-low power | en_US |
dc.subject | high-kappa | en_US |
dc.subject | Ge | en_US |
dc.subject | CMOS | en_US |
dc.subject | flash memory | en_US |
dc.title | Ultra-Low Power Green Electronic Devices | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | en_US |
dc.citation.spage | 285 | en_US |
dc.citation.epage | 288 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380458700072 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |