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dc.contributor.authorHsieh, Yu-Shengen_US
dc.contributor.authorShen, Ting-Tingen_US
dc.contributor.authorChien, Yu-Sanen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.contributor.authorShinozaki, Yukoen_US
dc.contributor.authorKawasaki, Naohikoen_US
dc.date.accessioned2017-04-21T06:49:30Z-
dc.date.available2017-04-21T06:49:30Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-8364-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/135770-
dc.description.abstractLow temperature (< 180 degrees C) Cu/In bonding scheme in wafer-level is successfully developed. The bonded sample represents robust bonding quality and passes mechanical tests. The inter-diffusion mechanism and IMC phases are investigated by EDX and EELS. In addition, the specific contact resistance of Cu/In chip is measured approximately 3 x 10(-9) Omega-cm(2) by modified Kelvin feature, demonstrating excellent electrical characteristics. Good stability is also observed from reliability tests, including current stressing, TCT and un-bias HAST. Therefore, this low temperature Cu/In bonding scheme provides a promising method for dense vertical interconnects.en_US
dc.language.isoen_USen_US
dc.subject3D integrationen_US
dc.subjectLow temperature eutectic bondingen_US
dc.subjectCu/In interconnecten_US
dc.titleInvestigation of Low Temperature Cu/In Bonding in 3D Integrationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)en_US
dc.citation.spage383en_US
dc.citation.epage386en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380458700097en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper