Investigation of Low Temperature Cu/In Bonding in 3D Integration

Abstract

Low temperature (< 180 degrees C) Cu/In bonding scheme in wafer-level is successfully developed. The bonded sample represents robust bonding quality and passes mechanical tests. The inter-diffusion mechanism and IMC phases are investigated by EDX and EELS. In addition, the specific contact resistance of Cu/In chip is measured approximately 3 x 10(-9) Omega-cm(2) by modified Kelvin feature, demonstrating excellent electrical characteristics. Good stability is also observed from reliability tests, including current stressing, TCT and un-bias HAST. Therefore, this low temperature Cu/In bonding scheme provides a promising method for dense vertical interconnects.