標題: Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection
作者: Liao, Seian-Feng
Tang, Kai-Neng
Ker, Ming-Dou
Yeh, Jia-Rong
Chiou, Hwa-Chyi
Huang, Yeh-Jen
Tsai, Chun-Chien
Jou, Yeh-Ning
Lin, Geeng-Lih
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2015
摘要: Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-mu m HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.
URI: http://hdl.handle.net/11536/135942
ISBN: 978-1-4799-9877-7
期刊: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD)
起始頁: 185
結束頁: 188
顯示於類別:會議論文