標題: Electrical Characteristic and Power Consumption Fluctuations of Trapezoidal Bulk FinFET Devices and Circuits Induced by Random Line Edge Roughness
作者: Chen, Chieh-Yang
Huang, Wen-Tsung
Li, Yiming
資訊工程學系
Department of Computer Science
關鍵字: Line edge roughness;fin-;resist-;spacer-;sidewall-;gate-LER;trapezoidal bulk FinFET;digital circuit
公開日期: 2015
摘要: In this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. By using a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFETs. The resist-LER is most influential on characteristic fluctuation. For the same type, spacer-LER has at least 85 % improvement on sigma V-th compared with resist-LER. As for the digital circuit characteristic, the rectangle-shape bulk FinFET has larger timing fluctuation.
URI: http://hdl.handle.net/11536/135975
ISBN: 978-1-4799-7581-5
ISSN: 1948-3287
期刊: PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)
起始頁: 61
結束頁: 64
Appears in Collections:Conferences Paper