Mismatch-Tolerant Time Amplifier with Embedded Self-Calibration

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lai, Jung-Chin	en_US
dc.contributor.author	Hsu, Terng-Yin	en_US
dc.date.accessioned	2017-04-21T06:48:22Z	-
dc.date.available	2017-04-21T06:48:22Z	-
dc.date.issued	2015	en_US
dc.identifier.isbn	978-1-4799-8748-1	en_US
dc.identifier.uri	http://hdl.handle.net/11536/136006	-
dc.description.abstract	This paper presents a reliable self-calibration scheme to reduce the mismatches of SR-Latch based 6X time amplifier (TA) to enhance the resolution of time-to-digital converter (TDC). The proposed calibration is embedded to compensate for process, voltage and temperature (PVT) variations that it can eliminate the gain error caused by input mismatches. With the proposed TA, a standard cyclic TDC implemented in UMC 65-nm CMOS process shows that the resolution is 1.25ps.	en_US
dc.language.iso	en_US	en_US
dc.subject	Reliable	en_US
dc.subject	TA	en_US
dc.subject	Mismatch	en_US
dc.subject	Calibration	en_US
dc.subject	TDC	en_US
dc.title	Mismatch-Tolerant Time Amplifier with Embedded Self-Calibration	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2015 IEEE 5TH INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - BERLIN (ICCE-BERLIN)	en_US
dc.citation.spage	393	en_US
dc.citation.epage	396	en_US
dc.contributor.department	資訊工程學系	zh_TW
dc.contributor.department	Department of Computer Science	en_US
dc.identifier.wosnumber	WOS:000380452700085	en_US
dc.citation.woscount	0	en_US
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