完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hsieh, E. R. | en_US |
dc.contributor.author | Huang, Z. H. | en_US |
dc.contributor.author | Chung, Steve S. | en_US |
dc.contributor.author | Ke, J. C. | en_US |
dc.contributor.author | Yang, C. W. | en_US |
dc.contributor.author | Tsai, C. T. | en_US |
dc.contributor.author | Yew, T. R. | en_US |
dc.date.accessioned | 2017-04-21T06:48:18Z | - |
dc.date.available | 2017-04-21T06:48:18Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4673-9894-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136035 | - |
dc.description.abstract | For the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<50 mu A), fast speed (similar to 20 mu sec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380472500013 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |