完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHsieh, E. R.en_US
dc.contributor.authorHuang, Z. H.en_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorKe, J. C.en_US
dc.contributor.authorYang, C. W.en_US
dc.contributor.authorTsai, C. T.en_US
dc.contributor.authorYew, T. R.en_US
dc.date.accessioned2017-04-21T06:48:18Z-
dc.date.available2017-04-21T06:48:18Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-9894-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/136035-
dc.description.abstractFor the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<50 mu A), fast speed (similar to 20 mu sec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era.en_US
dc.language.isoen_USen_US
dc.titleThe Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdownen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380472500013en_US
dc.citation.woscount0en_US
顯示於類別:會議論文