標題: The Demonstration of Gate Dielectric -fuse 4kb OTP Memory Feasible for Embedded Applications in High -k Metal-gate CMOS Generations and Beyond
作者: Hsieh, E. R.
Chang, C. W.
Chuang, C. C.
Chen, H. W.
Chung, Steve S.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2019
摘要: A 4kb macro of One Time Programming (OTP) memory, implemented by a new breakdown, named dielectric fuse (dFuse) breakdown, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 1.5T per cell with 7.5F2. The experimental results show that dFuse macro exhibits high programming (PGM) speed of 100ns at 4V, read time smaller than lOns at 0.75V, and excellent data retention under one -month baking at 150 C. More importantly, the program voltage is weakly dependent on the environmental temperature, suitable for automotive applications. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the storage purpose in loT and 5G era.
URI: http://hdl.handle.net/11536/154286
ISBN: 978-4-86348-718-5
期刊: 2019 SYMPOSIUM ON VLSI CIRCUITS
起始頁: 0
結束頁: 0
顯示於類別:會議論文