Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swing

Full metadata record

DC Field	Value	Language
dc.contributor.author	Kuo, Po-Yi	en_US
dc.contributor.author	Lin, Jer-Yi	en_US
dc.contributor.author	Chao, Tien-Sheng	en_US
dc.date.accessioned	2017-04-21T06:48:18Z	-
dc.date.available	2017-04-21T06:48:18Z	-
dc.date.issued	2015	en_US
dc.identifier.isbn	978-1-4673-9894-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/136036	-
dc.description.abstract	The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (D-NW) - length (L-NW) x width (W-NW) x thickness (T-NW) - to 80nmx13nmx3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) similar to 61mV/dec., steep driving swing (D.S.) similar to 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.	en_US
dc.language.iso	en_US	en_US
dc.title	Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swing	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)	en_US
dc.contributor.department	電子物理學系	zh_TW
dc.contributor.department	Department of Electrophysics	en_US
dc.identifier.wosnumber	WOS:000380472500033	en_US
dc.citation.woscount	0	en_US
Appears in Collections:	Conferences Paper