完整後設資料紀錄
DC 欄位語言
dc.contributor.authorKuo, Po-Yien_US
dc.contributor.authorLin, Jer-Yien_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2017-04-21T06:48:18Z-
dc.date.available2017-04-21T06:48:18Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-9894-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/136036-
dc.description.abstractThe implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (D-NW) - length (L-NW) x width (W-NW) x thickness (T-NW) - to 80nmx13nmx3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) similar to 61mV/dec., steep driving swing (D.S.) similar to 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.en_US
dc.language.isoen_USen_US
dc.titleImplantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000380472500033en_US
dc.citation.woscount0en_US
顯示於類別:會議論文