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dc.contributor.authorLee, Yao-Jenen_US
dc.contributor.authorHou, Fu-Juen_US
dc.contributor.authorChuang, Shang-Shiunen_US
dc.contributor.authorHsueh, Fu-Kuoen_US
dc.contributor.authorKao, Kuo-Hsingen_US
dc.contributor.authorSung, Po-Jungen_US
dc.contributor.authorYuan, Wei-Youen_US
dc.contributor.authorYao, Jay-Yien_US
dc.contributor.authorLu, Yu-Chien_US
dc.contributor.authorLin, Kun-Linen_US
dc.contributor.authorWu, Chien-Tingen_US
dc.contributor.authorChen, Hisu-Chihen_US
dc.contributor.authorChen, Bo-Yuanen_US
dc.contributor.authorHuang, Guo-Weien_US
dc.contributor.authorChen, Henry J. H.en_US
dc.contributor.authorLi, Jiun-Yunen_US
dc.contributor.authorLi, Yimingen_US
dc.contributor.authorSamukawa, Seijien_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.authorTseng, Tseung-Yuenen_US
dc.contributor.authorWu, Wen-Faen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.contributor.authorYeh, Wen-Kuanen_US
dc.date.accessioned2017-04-21T06:48:19Z-
dc.date.available2017-04-21T06:48:19Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-9894-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/136038-
dc.description.abstractWe propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.en_US
dc.language.isoen_USen_US
dc.titleDiamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department電機學院zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380472500095en_US
dc.citation.woscount0en_US
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