Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Yao-Jen | en_US |
dc.contributor.author | Hou, Fu-Ju | en_US |
dc.contributor.author | Chuang, Shang-Shiun | en_US |
dc.contributor.author | Hsueh, Fu-Kuo | en_US |
dc.contributor.author | Kao, Kuo-Hsing | en_US |
dc.contributor.author | Sung, Po-Jung | en_US |
dc.contributor.author | Yuan, Wei-You | en_US |
dc.contributor.author | Yao, Jay-Yi | en_US |
dc.contributor.author | Lu, Yu-Chi | en_US |
dc.contributor.author | Lin, Kun-Lin | en_US |
dc.contributor.author | Wu, Chien-Ting | en_US |
dc.contributor.author | Chen, Hisu-Chih | en_US |
dc.contributor.author | Chen, Bo-Yuan | en_US |
dc.contributor.author | Huang, Guo-Wei | en_US |
dc.contributor.author | Chen, Henry J. H. | en_US |
dc.contributor.author | Li, Jiun-Yun | en_US |
dc.contributor.author | Li, Yiming | en_US |
dc.contributor.author | Samukawa, Seiji | en_US |
dc.contributor.author | Chao, Tien-Sheng | en_US |
dc.contributor.author | Tseng, Tseung-Yuen | en_US |
dc.contributor.author | Wu, Wen-Fa | en_US |
dc.contributor.author | Hou, Tuo-Hung | en_US |
dc.contributor.author | Yeh, Wen-Kuan | en_US |
dc.date.accessioned | 2017-04-21T06:48:19Z | - |
dc.date.available | 2017-04-21T06:48:19Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4673-9894-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136038 | - |
dc.description.abstract | We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380472500095 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |